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list ordered chronologically from newest to oldest by project start
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date: 2025-11 to 2025-12
desc: first complex analog project, great success
proj: https://github.com/sarvl/analog-audio-amplifier
date: 2024-06 - 2024-10; on and off throughought 2025; 2026-06 - WIP
desc: fourth CPU design, significantly bigger project scope ; WIP
proj: https://github.com/sarvl/16b4x
This post is sponsored by PCBWay!
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date: 2023-04 to 2023-09 ; 2023-12 to 2024-01 ; 2024-04 to 2024-05
desc: third CPU design, vastly more complicated than previous designs ; implemented cache, pipelining, out of order execution
proj: https://github.com/sarvl/16b3x
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date: 2022-05 ; 2023-01 ; 2023-04
desc: second CPU design, mostly fixes from previous designs ; implemented unified memory ; first CPU written in VHDL
proj: https://github.com/sarvl/16b2x
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date: 2022-02-22 (yes, single day)
desc: first CPU ever done, HEAVILY inspired by UCB CS61C, contains massive mistakes and bad design decisions
proj: https://github.com/sarvl/16b1x
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