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16b1x CPU

date: 2022-02-22 (yes, single day)
desc: first CPU ever done, HEAVILY inspired by UCB CS61C, contains massive mistakes and bad design decisions
proj: not available, maybe will be, not sure

OVERVIEW

full image

as the name suggests, its 16bit cpu
the ISA is very simple and does not even utilize all space for instructions
design is pretty much copycat (not intentional!) of what was shown in course because that was all I knew at that time
it was complicated enough to get everything working without thinking about design too much, later projects radically improved on that side
instruction and data memory are split so every instruction takes exactly 1 cycle

CPU was implemented in logisim and I was assembler for longer than I would like to admit before writing proper one in c++

ISA

Instructions

mvr Rd, Rs # Rd <-- Rs
mvi Rd, imm8 # Rd <-- imm8
lod Rd, Rs # Rd <-- M[Rs]
str Rd, Rs # M[Rs] <-- Rs
add Rd, Rs # Rd <-- Rd + Rs
sub Rd, Rs # Rd <-- Rd - Rs
and Rd, Rs # Rd <-- Rd & Rs
or Rd, Rs # Rd <-- Rd | Rs
xor Rd, Rs # Rd <-- Rd ^ Rs
not Rd, Rs # Rd <-- ~ Rs
sll Rd, Rs # Rd <-- Rd << Rs
srl Rd, Rs # Rd <-- Rd >> Rs
jnz Rd, imm8 # if(Rd != 0) PC <-- imm8

Instruction Format

r-format

	15    12 11  8 7   6 5      0
	[OPCODE] [Rd ] [Rs ] [UNUSED]

i-format

	15    12 11  8 7    0 
	[OPCODE] [Rd ] [IMM8]

note: ^ this is wrong, see THE BAD

Registers

all are 16bit

Z hardwired to 0
A GP 0
B GP 1
C GP 2
D GP 3
E GP 4
F GP 5
SP Stack Pointer (not special from HW POV)

Example Program


	mvi 	A, 0x0
	mvi 	B, 0x1

#(n + 2)th fib number
	mvi 	E, 0x5
#to be able to subtract one
	mvi 	F, 0x1

LABEL loop
	#C = A + B
	mvr 	C, A
	add 	C, B

	#A = B
	mvr 	A, B
	#B = C
	mvr 	B, C

	#M[0] = C
	str 	C, ZERO

	#E -= F
	sub 	E, F

	jnz 	E, loop

THE GOOD

the very best thing is that it works

its hard to find any other thing that is noteworthy good
at the time I was proud of using mux to select correct control signals instead of combinational logic
later I realized that not only this is quite common, I shouldve used ROM component directly

THE BAD

the worst thing in this design is that somehow a bit was skipped
instruction format shown previously has bits 11:8 assigned for Rd, its 4 not 3, Rs has bits 7:6, its 2 not 3
correct thing would be Rd - 11:9, Rs - 8:6
for r-format its not so bad as total bit count states the same but immediate has wasted bit that is not used for anything for no reason
since r-format and i-format have unused bits then this additional bit could be used to select between reg/immediate as second operand and it would be way more convientient to code
later designs fixed this issue in exactly this way
I became aware of this while wiring control, I was tired already so I decided that I dont care

zero register is completely useless and terribly inefficient idea for cpu with 8 registers in total
it was kind of needed because of lack of immediate operand for every instruction (see paragraph above)
nonetheless, if it was needed then simple mvi Rd, 0 would suffice and would not waste register regardless of input

THE UGLY

ISA mentions SP but it was not used as no instructions that utilize it were implemented
similarly local isa.txt mentions memory regions but again, it was not implemented

seperated data/instruction memory was ok at the time but was suboptimal and later designs changed it
in fact, main purpose of 2nd iteration was to unify memory and fix terrible mistakes here

0x0000 should not be mvr Z, Z becaues of NOP slide
unfortunatelly I became aware of this fairly recently and so 2 next designs also feature this problem
this is not that bad for architecture that was not design for serious use which is why its in this section and not THE BAD

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